`timescale 1ns / 1ps 
module tb();
    reg rst, clk;   
    reg write_arbition;  
    wire data_en;
    wire [31:0] data;
    wire [5:0] data_priority;
    wire [5:0] data_target_port;
    wire [9:0] data_wait_time;
    wire data_write_en;
    wire [9:0] data_size;


    initial begin            
        $dumpfile("tb.vcd");        
        $dumpvars(0, tb);    
    end

    initial begin
        rst = 1;
        clk = 1;
        forever begin
            #10 clk = ~clk;
        end
    end


    initial begin
        #30
        rst <= 0;
    end

    initial
        #20000 $finish;

    reg [9:0] dataSeed;

    initial begin
        dataSeed <= 289;
    end

    initial begin
        #40
        write_arbition <= 1;
        #20
        write_arbition <= 0;
    end

    dataGenerator gen(.clk(clk), .rst(rst), 
                    .write_arbition(write_arbition), .seed(dataSeed), .data_ready(data_en), .data(data), 
                    .data_priority(data_priority), .data_target_port(data_target_port), .data_wait_time(data_wait_time), .data_write_en(data_write_en), .data_size(data_size));

    portOut port(.clk(clk), .rst(rst), .date_en(data_en), .data_in(data), 
                .port_idle(), .sop(), .eop(), .data_out());
endmodule